This invention relates generally to reducing power consumption in computers, and more particularly to power conservation without performance reduction in a power-managed system.
Portable and lap-top computers have become widely used and are increasing in popularity. An advantage of such computers is that they can be operated with the use of batteries without the need for an external power supply. A limitation faced by these portable computers is that their batteries have a limited life. A typical battery pack generally needs to be recharged after every two-to-four hours of use. Thus, an efficient power management scheme is essential in order to allow these computers to run as long as possible without requiring the recharging of their batteries. Power management has also become an issue with respect to desktop and floor-standing computers because it is increasingly important to build environmentally friendly computers that consume less power. In addition, reduced power consumptions also lowers heat dissipation and increases the reliability of a system.
A common method for power management for portable computing systems and environmentally friendly desktops and floor-standing systems currently involves the reduction of the processor clock speed, either during periods of inactivity or on a continuous basis. The performance of a computing system is largely determined by the speed at which the processor can read and write to system memory. In many computing systems, performance is enhanced through the use of a high-speed memory cache, external to the processor, that minimizes the performance impact of using slower memory, such as dynamic random access memory (DRAM), for the system memory.
In many power-managed systems, an external, high-speed memory cache is not employed due to power, space or cost limitations. This means that the performance of the system is largely determined by how many clock cycles are required for the processor to read from and write to the system memory. The number of clock cycles required is constant in today""s systems and is based on the minimum number of complete clock cycles (or partial clock cycles in some specialized systems) that are needed to meet the worst-case access timing of the system memory subsystem when the processor is running at its maximum speed. In power-managed computing systems that employ processor clock speed reduction for power management, the number of clock cycles used for system memory access, at reduced clock speeds, remains the same.
Based on this prior art technology, better power consumption management in computerized systems is always desirable; hence, any power consumption management strategy that extends battery life without reducing performance is useful for implementation in computerized systems.
The above-identified needs as well as other needs, shortcomings and problems are addressed by the present invention, which will be understood by reading and studying the following specification. The invention describes the conservation of power while minimally reducing performance in a power-managed computer system. In one embodiment of the invention, a method includes three steps. In the first step, the nature of the computer program is determined. The program has a nature selected from the group essentially consisting of substantially memory-intensive and substantially computer-intensive. In the second step, the clock speed of the computer system is increased and the number of memory access wait states of the computer system is adjusted incident to determining that the nature of the computer program is substantially computer-intensive. In the third step, the clock speed of the computer system is decreased and the number of memory access wait states of the computer system is decreased incident to determining that the nature of the computer program is substantially memory-intensive.
Thus, compute-intensive activities running on a computer system are run at full processor speed while memory-intensive activities are run at a reduced processor speed. Desirably, while the computer is running at this reduced speed, the memory wait states are adjusted so that memory subsystem access occur at the same speed as they would at full processor speed. This results in power savings with little or no performance reduction.
In different embodiments of the invention, methods, computers (i.e., information handling systems), and computer-readable storage media of varying scope are described. Still other and further embodiments, aspects and advantages of the invention will become apparent by reference to the drawings and by reading the following detailed description.